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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? 15 ma rms output ? 11.8 v l-l synchro, 11.8 v l-l resolver, or 6.81 v l-l resolver output ? 8 bit/2 byte double-buffered transparent latches ? pin programmable for synchro or resolver output ? 16-bit resolution ? complete d/s and d/r converter ? mate to dsc-36020 ibm? pc card ? dc-coupled reference accepts any waveform ? generates sin/cos dc or rotating ppi sweep ? high-rel cmos d/r chip ? no +5 v supply required ? lvdt simulation description the dsc-11524 is a versatile multiplying digital-to-synchro/resolver converter. the digital input represents an angle, and the output is pin programmable for either resolver, sin/cos, or three-line synchro type output. the reference input will accept any waveform, even a sawtooth for crt drive. because the reference is dc coupled to the output, the dsc-11524 can be used in many configurations, such as: a digital-to-synchro/resolver converter using a sinusoidal reference as an input; a digital-to-sin/cos dc converter using a dc reference; a polar-to- rectangular converter using a reference input proportional to the radius vector; a rotating cartwheel sweep generator for ppi displays using a sawtooth refer - ence. packaged in a 36-pin ddip, the dsc-11524 is a complete d/s and d/r con - verter in one hybrid module. hybrid technology results in low weight, low power consumption, very high reliability, and a wide operating temperature range. the dsc-11524 circuit design allows for higher accuracy and reduces the output scale factor variation so that the output can drive displays directly. the output line-to-line voltage can be scaled by external resistors. other features include high ac and dc common mode rejection at the reference input, and output short circuit protection. applications because of its high reliability, small size and low power consumption the hybrid dsc-11524 is ideal for the most stringent and severe industrial and military ground or avionics applications. all units are available with mil-prf-38534 pro - cessing as a standard option. among the many possible applications are computer-based systems in which digital information is processed, such as simulators, flight trainers, flight instru - mentation, fire control systems, radar and navigation systems, and ppi displays including moving target indicators. dsc-11524 16-bit hybrid d/s and d/r converter pin programmable for synchro or resolver output make sure the next card you purchase has... ? 1998, 1999 data device corporation all trademarks are the property of their respective owners.
2 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 figure 1. dsc-11524 block diagram reference inputs 26 v adjustable 1.3-26 v 100 k 100 k 5 k 5 k d/r converter high accuracy low scale factor variation electronic scott-t or resolver scaling output amplifiers s1 s2 s2 s3 s3 s4 synchro or resolver output (pin jumper programmable) bits 9-16 bits 1-8 digital inputs bits 1-16 lm la ll test point -r transparent latch transparent latch reference conditioner rh/rl rh'/rl'
3 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 -55 to +125 0 to +70 -55 to +135 c c c tempera ture ranges (case) operation ? -1 option ? -3 option storage table 1. dsc-11524 specifica tions apply over temperature range, power supply range, reference voltage and frequency range, and 10% harmonic distortion in the reference. p arameter unit value bits 16 resolution minutes lsb sec accuracy and dy namics output accuracy differential linearity output setting time 4 to 2 min. (see ordering information.) 1 max less than 20 for any digital step change a digit al input logic type logic voltage level load current natural binary angle, parallel positive logic cmos and ttl compatible. inputs are cmos transient protected. logic 0 = 0 to +0.8 v logic 1 = 2 v to 1/3 of v dd +10% 20 max (bits 1-16) 65 max ( ll , lm , la ) see timing diagrams (figures 2a/2b.). hz v k ohm k ohm reference input type frequency range voltage input impedance ? single ended ? differential two differential solid-state inputs: one for standard 26 v, one programmable. dc to 1k standard input p rogrammable input 26 (note 1) 100 0.5% 200 0.5% 1.3 minimum for full output; higher voltages are scaled by adding two series resistors 5 0.5% 10 0.5% ma rms vrms l-l vrms l-l % % mv analog output type output current output voltage ? synchro mode ? resolver mode transform. ratio tol. scale factor varation dc offset (each line to gnd) pin programmable for synchro or resolver 15 max (tracks reference input voltage) 11.8 nominal 6.81 or 11.8 nominal 0.5 max 0.1 max 15 max. varies with input angle. v ma po wer supplies voltage max voltage without damage max current or impedance +15 5% +18 v 35+ load current -15 5% -18 v 35+ load current 36-pin ddip 0.78 x 1.9 x 0.21 (19.7 x 48.3 x 5.3) 0.85 (24) in.(mm) oz. (g) physical ch aracteristics type size weight notes: 1) maximum reference input voltage for rh/rl is 26 v +10%. 2) differential is line-to-line (l-l); single-ended is line-to-ground (l-gnd).
4 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 introduction as shown in figure 1, the signal conversion in the dsc-11524 is performed by a high-accuracy digital-to-resolver converter whose sin and cos outputs have a low scale factor variation as a function of the digital input angle. this resolver output is either amplified by scaling amplifiers for resolver output, or is both amplified and converted to a synchro output by an electronic scott-t. in both cases the output line currents can be 15 ma rms max, which is sufficient for driving s/d converters, solid-state control transformers and displays. output power amplifiers will be required, however, for driving electromechanical devices such as synchros and resolvers. the reference conditioner has a differential input with high ac and dc common mode rejection, so that a reference isolation transformer will seldom be required. there are two sets of refer - ence inputs. the rh, rl input provides the maximum synchro or resolver output voltage for a standard 26 v rms reference input. the rh, rl input is used to scale the output for other reference voltage levels. series resistors can be added to the reference input as described below, either to accommodate higher refer - ence levels, or to reduce the output level. the reference condi - tioner output -r is intended for test purposes. a signal between 6 v and 7.5 v at -r indicates that a reference input signal is pres - ent. digital input the converter contains three input latches. the input is con - trolled by lm and ll . each of these enable the converter to interface with an 8-bit bus. lm controls bits 1-8 and ll controls bits 9-16. ensure that the data is stable for 50ns before enabling a latch ( ll , lm ), and allow 100ns for the latch to input the data. input bit weights are as follows: bit 1, msb = 180 degrees bit 16, lsb = 0.0054 degrees (see table 2) power supply cycling power supply cycling of the ddc converter should follow the guidelines below to avoid any potential problems. strictly maintain proper sequencing of supplies and signals per typical cmos circuit guidelines: - apply power supplies first (+15v, -15v and ground). - apply analog signals last. the reverse sequence should be followed during power down of the circuit. 16 bit digit al w ord ( ) (1 = msb, 16 = lsb) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 degrees (hex) 0 (0000) 15 (0aab) 30 (1555) 45 (2000) 60 (2aab) 75 (3666) 90 (4000) 120 (5555) 135 (6000) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 180 (8000) 240 (aaab) 270 (c000) 285 (caab) 300 (d555) 315 (e000) 330 (eaab) 345 (f555) 359 (ffff) 0 table 2. a n gles in degrees cross referenced t o a 16-bit digit al w ord 0
5 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 r' = 5k 1.3 (v rh' rl' x nom v ll desired v ll - 1.3) v rh' rl' = reference input voltage to pins 11 & 9 nomv ll = analog output voltage (l-l) configuration as per figure 4 desired v ll = scaled analog output voltage example to scale reference input rh'/rl' to 115 vrms (configured for 11.8v nominal output) r' = r' 437k? 5k 1.3 (115 x 11.8 11.8 r' r' rh' pin 11 dsc-11524 rl' pin 9 11.8v l-l output 115v example to scale output voltage line-to-line of 9 volts (configured for 115v reference input ) r' = r' = 575 k? 5k 1.3 (115 x 11.8 9 r' r' rh' pin 11 dsc-11524 rl' pin 9 9 v l-l output 115v output voltage scaling without external r' resistors. the output voltage can be scaled down from the nominal voltage l-l. input/output ratio is 0.45 for the rh/rl 26v reference input. example to scale a 9v l-l output using the 26v rh/rl reference voltage on input pins 10 & 8. ref input voltage = desired output (l-l) 0.45 9 0.45 = ref input voltage = 19.8v r' r' rh' pin 10 dsc-11524 rl' pin 8 9 v l-l output 19.8v - 1.3) - 1.3) output scaling and ref level adjustment the dsc-11524 operates like a multiplying d/a converter in that the voltage of each output line is directly proportional to the refer - ence voltage. the maximum line-to-line levels are determined by the output amplifiers and are nominally 11.8 v for synchro output and 6.81 v or 11.8 v for resolver output. the rh, rl reference input is designed to provide this nominal output for the standard 26 v reference level. the scaling adjustment is made by two internal 100k ohm resistors in series with the reference condi - tioner input (see figure 1). the rh, rl reference input has only 5k ohm internal resistors in series with the reference conditioner input, so that nominal line-to-line output is obtained for a reference input of 1.3 v. for higher reference voltages, two resistors, r, must be inserted in series with the inputs. these resistors scale the dsc-11524 to accommodate higher reference levels, or to reduce the output levels. the magnitude of the resistors, r, in ohms is calculated as follows:
6 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 200 ns min. transp arent la tched d ata 1-16 bits 125 ns min. wi th la se t lo = 125ns mi n wi th ll, lm , la ti ed t oget her = 200ns mi n data changing data stab le data changing data stab le 125 ns min. 125 ns min. 125 ns min. 125 ns min. 200 ns min. 200 ns min. ll lm la d ata bits (9-16) bits (1-8) 200 ns min. la, lm, ll tr ansparent = hi latched = lo 200 ns figure 2a. ll , lm , la timin g diagram (16-bit) figure 2b. ll , lm , la timin g diagram (8-bit)
7 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 output configuration the output amplifier section can be configured for synchro and resolver outputs, as shown in figure 3. output phasing and output scale factor the analog output signals have the following phasing: synchro output: s3s1 = (rh - rl)a o (1 + a( )) sin s2s3 = (rh - rl)a o (1 + a( )) sin( + 120) s1s2 = (rh - rl)a o (1 + a( )) sin( + 240) resolver output: s3s1 = (rh - rl)a o (1 + a( )) sin s2s4 = (rh - rl)a o (1 + a( )) cos the output amplifiers simultaneously track reference voltage fluctuations because they are proportional to (rh - rl). the transformation ratio a o is 11.8/26 for 11.8 v rms l-l output. the maximum variation in a o from all causes is 0.5%. the term a( ) represents the variation of the amplitude with the digital signal input angle. a( ), which is called the scale factor variation, is a smooth function of ( ) without discontinuities and is less than 0.1% for all values of ( ). the total maximum variation in a o (1 + a( )) is therefore 0.6%. because the amplitude factor (rh - rl)a o (1 + a( )) varies simul - taneously on all output lines, it will not be a source of error when the dsc-11524 is to drive a ratiometric system such as a syn - chro or resolver. however, if the outputs are used independently, as in x-y plotters, the amplitude variations must be taken into account. output transformer the dsc-11524 uses the 51538 step-up transformer to drive 90 v l - l synchro loads. the 51538 transformer specifications are shown in table 3 and the schematic and mechanical outline drawings are shown in figure 4. figure 3. output pin p rogramming 34 s3 35 s3 s3 (sin) 32 s1 s1 (sin) dsc-11524 36 s2 s2 (cos) 31 s4 s4 (cos) 33 s2 11.8 v resolver ou tput 32 35 s1 s1 s3 +sin 36 s2 s2 33 36 dsc-11524 s2 dsc-11524 s2 +cos 35 s3 s3 34 33 s3 s2 rtn * 11.8 v sy nch ro output 6.81 v resolver ou tput ? ? ? ? *for s2(z) grounded applications use beta transformer p/n 42929, synchro-to-synchro, 11.8v to 11.8v 400 hz.
8 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 figure 4. 90 v l-l , 400 hz synch ro outpu t transformer (p/n 51538) 7 1.63 max (41.40) 1 2 3 8 4 5 6 0.40 (10.16) 0.800 (20.32) 0.40 (10.16) 0.200 (5.08) 8 places 1.130 max (28.702) 1.00 (25.4) 2 0.042 dia pin ) 0.23 min (5.842) bottom view side view dot this side side opposite pin 1 marking 0.510 max (12.954) +0.076 -0.102 +0.003 -0.102 (1.067 0.800 (20.32) synchro output (90v) synchro output (11.8v) s1 s3 1 t1a t1b 5 6 3 7 s2 s1 s2 s3 synchro input 11.8 vrms line-to-line 10% at 400 hz 10% synchro output 90 vrms 1% full scale with a line-to-line input voltage of 11.8 vrms input impedance 1000 ohms minimum output impedance 500 ohms maximum accuracy the maximum additional error shall be 1.5 min. loaded with an sdc-14560 (130k ohm) hipo t between windings and windings-to-case 900 vrms at 60 hz t able 3. elec t rical specifica tion s for th e 51538 transformer
9 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 1.895 C0.005 (48.1 C0.13) 1.700 C0.005 (43.2 C0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) contrasting colored bead identifies pin 1 0.775 C0.005 (19.7 C0.13) 0.600 C0.005 (15.2 C0.13) 0.09 C0.01 (2.3 C0.25) 0.10 C0.01 (2.5 C0.3) side view bottom view 0.25 min (6.4) 0.015 max (0.39) seating plane 0.055 (1.4) rad typ 0.086 typ radius 18 1 19 36 notes: 1. dimensions shown are in inches (millimeters). 2. lead identification numbers are for referenced only. 3. lead cluster shall be centered within of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements of mil-std-202e, method 208c. 5. package is kovar with electroless nickel plating. 6. case is electrically floating. figure 5. dsc-11524 36- pin ddi p mechan ical outline t able 4. pin connectio n t able pin pin pin name name name 13 14 15 16 17 18 19 20 21 22 23 24 nc +15v gnd -15v nc nc -r rl rl rh rh bit 14 1 2 3 4 5 6 7 8 9 10 11 12 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 25 26 27 28 29 30 31 32 33 34 35 36 bit 1 (msb) bit 15 bit 16 (lsb) lm ll la s4 s1 s2 ' s3 ' s3 (+sin) s2 (+cos) notes: 1. -r (pin 7) can be used for test purposes to detect whether a reference signal is present. see block diagram. 2. functions ll, la, and lm may be left unconnected when not used. 3. nc, means no internal wire connection.
10 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 lvdt simulation to test an lvdt application using a synchro/resolver simulator, the angular bit weights of the r/d converter, in the linear mode, are modified as follows (also see table 5): bit 3: 0.5/0.5 = 1 arc tan (1) = 45 bit 4: 0.25/0.75 = 0.333 arc tan (0.333) = 18.435 bit 5: 0.125/0.875 = 0.143 arc tan (0.143) = 8.130 t able 5. angular bi t weights for lvd t simula tion d a t a bi t on angle 3 4 5 6 7 8 9 10 11 12 13 14 15 16 45 18.435 8.130 3.814 1.848 0.911 0.451 0.225 0.112 0.056 0.028 0.014 0.007 0.0035 dsc-11524 direct output mode digital angle input sin cos rtn va vb gnd ( 3 wire lvdt output ) } see % of travel column of table 5 } see table 4 data bit on figure 7. lvdt simula tion % of full t ravel .5(center null point) 0.333 0.143 0.0667 0.03226 0.01587 0.00787 0.00392 0.00196 0.00098 0.00049 0.00024 0.00012 0.00006 .707 50% full travel (b) b=d/r output simulating 50% travel sum = .707 + .707 = 1.4 1 0 travel (null) figure 6. lvdt output
11 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 rd-19230fx output 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 0 1 x x x x x x x x x x x x x x 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x x x x x x x x full scale msb lsbs 8 bit lsbs 14 bit lsbs 12 bit lsbs 10 bit lvd t output + o ver full scale + full t ravel - 1lsb +0.5 t ravel +1 lsb null - 1 lsb - 0.5 travel - full t ravel - over full scale use table 6 to read rd-19230fx outputs and relate to lvdt movement. .5 1 50% travel (a) a = lvdt output when @ 50% travel sum = .5 + .5 = 1 .707 50% full travel (b) b=d/r output simulating 50% travel sum = .707 + .707 = 1.4 1 0 travel (null) note: 2-wire lvdt outputs when summed equal a con - stant. the dsc-11524 sin & cos when summed will not be a constant. therefore to minimize rd-19230 gain effects full scale (i.e. 90 or 0 input to d/r) at the r-to-d should be 1.7 vrms instead of 2 vrms only when using a d-r converter for testing. note: a feedback circuit using the sin & cos sum to adjust rh-rl gain can be used to overcome this gain issue. table 6. digit al outpu t of rd-19230fx dsc-11524 direct output mode digital angle input sin cos rtn 3-wire lvdt input rd-19230 set up in lvdt mode, with lvdt front end ckt. lvdt digital data output va vb gnd figure 8. connecting t o an rd-19230fx conver ter figure 9. lvdt output vs d/r lvdt simula tion output note: see the rd/rdc mn-19220xx application manual for lvdt to digital conversion theory. these can be down - loaded from our website www.ddc-web.com.
12 data device corporation www.ddc-web.com dsc-11524 l-7/08-0 orderin g informa tion dsc-11524-xxxx supplemental p rocess requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and pre-cap source y = one lot date code and 100% pull test z = one lot date code, pre-cap source and 100% pull test blank = none of the above accuracy: 3 = 4 minutes 4 = 2 minutes p rocess requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b 1 3 = mil-prf-38534 compliant with pind testing 2 4 = mil-prf-38534 compliant with solder dip 2 5 = mil-prf-38534 compliant with pind testing and solder dip 2 6 = b 1 with pind testing 7 = b 1 with solder dip 8 = b 1 with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) t emperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data 1. standard ddc processing with burn-in and full temperature test see table below. 2. mil-prf-38534 product grading is designated with the following dash numbers: class h is a -11x, 13x, 14x, 15x, 41x, 43x, 44x, 45x class g is a -21x, 23x, 24x, 25x, 51x, 53x, 54x, 55x class d is a -31x, 33x, 34x, 35x, 81x, 83x, 84x, 85x these products contain tin-lead solder finish as applicable to solder dip requirements. table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test st an dard ddc p rocessing for hybrid and monolithic hermetic produc ts
13 l-7/08-0 printed in the u.s.a. ? u the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2426 for t echnical support - 1-800-ddc-5757 ext. 7771 h eadquarters, n .y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 w orld wide w eb - http://www.ddc-web.com

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